1. Field of the Invention
The invention relates to a full adder circuit for adding two n-bit binary numbers, i.e. to a full adder circuit divided into a plurality of cascaded sub-circuits of a first type having a plurality of bit inputs for receiving groups of bit signals having a significance progressing from m to k wherein m&lt;k.ltoreq.n. The sub-circuit of a first type comprises two sub-circuits of a second type and a selection circuit, first and second sub-circuits of the second type, respectively receiving the respective logic values "0" and "1" at a carry signal input and generating at a carry signal output an imaginary carry signal having a significance k+1. These carry signal outputs are connected to inputs of the selection circuit, a further input of which is connected to an output of a preceding sub-circuit of the first type or a sub-circuit of the second type which is arranged in cascade with the sub-circuit of the first type, at which output a carry signal having a first significance (m) is generated for selecting, with the aid of the selection circuit, a carry signal having a higher significance (k+ 1) from the generated imaginary carry signals and for applying the selected carry signal to a carry signal output of the sub-circuit of the first type.
2. Description of the Prior Art
Such a logic circuit is described in a publication disclosed during the International Solid State Conference, Feb. 22nd 1984, pages 90, 91, 324 "A CMOS Floating Point Multiplier" by Masaru Kya. The 24 bit-full adder circuit used in the multiplier circuit comprises, arranged in cascade, sub-circuits of a first type which each comprise two parallel-operating (4, 5 or 6 bits) full adder sub-circuits of a second type, respective first and second sub-circuits of the second type receiving a logic signal "0" and "1", respectively at their carry signal inputs. The two parallel-operating sub-circuits of the second type consequently generate complementary groups of sum signals and complementary imaginary carry signals. A first real carry signal is generated by a first full adder sub-circuit of the second type from the group of least significant bits of the two numbers to be added. The first real carry signal is applied to a multiplexing circuit of a sub-circuit of the first type, which is arranged in cascade with the first full adder sub-circuit of the second type by means of which a group of sum signals is selected from the complementary groups of sum signals applied to the multiplexing circuit. In addition, the sub-circuit of the first type comprises selection means to which the complementary imaginary carry signals are applied and also the first real carry signal. With the last-mentioned carry signal the correct carry signal of a higher significance is selected from the two imaginary carry signals, which in its turn is utilized as the "first real" transfer signal for a subsequent sub-circuit of the first type, arranged in cascade with the sub-circuit of the first type. Using such a full adder circuit it is possible to add together large binary numbers (for example 24-bit numbers) in a comparatively short time.
Due to the use of the dual full adder sub-circuits of the second type and the multiplexing circuit connected thereto, the circuit has the disadvantage that a comparatively large semiconductor surface is required. Moreover, the time necessary for adding together binary numbers of, for example, more than 32 to 40 bits, will increase because of the increasing number of series-arranged selection means (gate circuits) required therefor.